The present application claims priority to Japanese Application No. P11-215800 filed Jul. 29, 1999 which application is incorporated herein by reference to the extent permitted by law.
1. Field of the Invention
The present invention relates to a semiconductor device, more particularly, to a DRAM gain cell suitable for embedding with a logic circuit.
2. Description of the Related Art
In recent years, semiconductors have been becoming increasingly miniaturized. Not only are many elements embedded on a single chip, but also several functions have to be incorporated.
As a typical example of this, there is a LSI embedding both a DRAM and logic circuit.
By embedding not only a logic circuit but also a memory in an ASIC (application specific integrated circuit), the range of application of the ASIC is expanded.
At the present time, in a DRAM (dynamic random access memory), the most typical type of high density, high capacity semiconductor memory, as shown in FIG. 10, a memory cell is configured by connecting a transistor T controlled in on/off state by the potential of a word line WL and a memory capacitor MCAP in series between a bit line BL and common potential line SL.
In a one-transistor one-capacitor type memory cell MC, a connection point between the memory capacitor MCAP and the transistor T forms a storage node ND. The xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d of data is differentiated by a difference of the amount of a charge stored in this storage node.
It is necessary to cause a sufficiently large potential change in the bit line BL in order to secure stable operation when reading stored data. The capacity for storage of a charge (capacitance of the capacitor) is determined for the memory capacitor MCAP from this viewpoint.
Along with the reduction in the occupied area by a semiconductor memory cell, however, the capacitance value of the capacitor itself tends to fall. In addition, the increases in memory capacity have led to an increase in the bit line capacitance. Therefore, it is becoming even harder to obtain a readable bit line potential compared with the past.
As measures to solve this problem, various capacitor structures have been proposed such as a stack type, fin type, cylindrical type, or other stacked capacitor having a capacitor electrode increased in surface area per unit area and a trench capacitor etc.
However, due to the limits in processing technology on the aspect ratio of the trench formed on a substrate, the height of a stacked electrode layer, etc. or the increase of the number of process steps for forming a complex structure and the resultant increase in manufacturing cost etc., it is becoming difficult to increase the capacitance value of a capacitor per unit area.
On the other hand, the capacitance of a capacitor is proportional to the dielectric constant of a capacitor insulating film sandwiched between electrodes, so a capacitor insulation material with a high dielectric constant is also being developed.
In addition to the difficulty of development of a dielectric material itself, however, there are extensive development themes such as development of electrode materials with a good affinity with the dielectric or development of processing techniques for these new materials. Also, the development costs or newly introduced production equipment etc. pose an sizeable burden. As a result, the DRAM production cost has been continuously increasing. Therefore, even if the cell area is reduced and DRAMs are made larger in capacity, it is proving hard to reduce the cost per bit.
In view of this, when trying to reduce the cell area without changing the structure and materials, the reading signal of a DRAM cell becomes smaller, and, ultimately, it is expected that detecting data stored in the memory cell will become difficult.
Further, as a DRAM cell, in addition to the one-transistor one-capacitor type mentioned above, there is known for example a three-transistor type memory cell not using a capacitor and using three transistors. In this case, in addition to the two word lines for writing and reading, two bit lines for writing and reading besides are necessary so the number of Interconnection layers is increased.
However, a large number of interconnection layers may well become a limiting factor in reducing the cell area.
The present invention has been made to solve the above problems and has as its object to provide an inexpensive memory having a DRAM function. More particularly, when considering mounting together with a logic circuit, it is to provide a semiconductor device minimizing the effect on the logic process and enable realization of a hybrid circuit of a memory cell and peripheral circuit easily and at a low cost.
The semiconductor device according to the present invention comprises a memory cell having a plurality of active elements and at least one passive element.
Further, in the present invention, the plurality of active elements comprising the memory cell are field effect transistors having three terminals which comprise two diffusion layers forming a source or drain, and a gate or four terminals which comprise two diffusion layers forming a source or drain, a gate and a substrate or a layer which includes an area at which channel is formed, and the passive element comprising the memory cell is a capacitor having an insulating layer between a first electrode and a second electrode.
Further, in the present invention, the active elements comprising the memory cell include at least a transistor having a function of writing data and a transistor having a function of reading data.
Further, in the present invention, the memory cell comprises two field effect transistors and one capacitor, a first field effect transistor is an N-channel type or P-channel type, and a second field effect transistor is also an N-channel type or P-channel type.
Further, in the present invention, the memory cell is configured by a second diffusion layer terminal of the first field effect transistor, the second electrode of the capacitor, and a gate electrode terminal of the second field effect transistor connected together and, further, the first electrode of the capacitor is connected to a word line, a first diffusion layer terminal of the first field effect transistor is connected to a bit line, a gate terminal of the first field effect transistor is connected to a control gate line, a first diffusion layer terminal of the second field effect transistor is connected to the bit line, and a second diffusion layer terminal of the second field effect transistor is connected to a predetermined power supply terminal.
Further, in the present invention, at least one of the first electrode and second electrode of the capacitor serves also as an interconnection layer.
Further, in the present invention, all of the active elements comprising the memory cell are N-type field effect transistors or P-type field effect transistors.
Further, in the present invention, when arranging the memory cell in an array, the gate electrode terminal of the first field effect transistor of each of a plurality of memory cells connected to one word line is connected to one control gate line.
Further, in the present invention, when arranging the memory cell in an array, the gate electrode terminal of the first field effect transistor of each of the plurality of memory cells connected to one bit line is connected to one control gate line.
Further, in the present invention, the memory cell is embedded with a logic circuit.
According to the present invention, the stored charge of the passive element, for example, capacitor, may be one of an extent enabling control of the on/off state of an active element, that is, first field effect transistor (read transistor), in accordance with the stored data.
Therefore, in this memory cell, since there is no need for directly charging and discharging a large capacity bit line by the stored charge of the capacitor such as with a one-transistor one-capacitor type DRAM, the capacity of charge storage of the capacitor can be made small.
At a result, in a memory cell of this structure, it is not necessary to tinker with the capacitor structure to increase the amount of charge storage per unit area or to develop a capacitor dielectric material of a high dielectric constant. That is, since the structure is not complex, it is easy to make and further there is no rise in the production cost along with complication of the process.
Further, since there is one bit line, the cell area is small, and the degree of integration can be made higher and since a logic transistor can be used without any major change, the compatibility with the CMOS logic process is good and it is possible to mount a DRAM function together with a logic circuit by few processes.